1. Field of the Invention
This invention generally relates to integrated circuits, and more particularly to devices allowing voltage multiplication.
2. Description of the Prior Art
The invention finds many applications in the field of microelectronics, and in particular in the decoding of rows of DRAM memory cells, or else in the production of charge pump devices.
The supply voltages of integrated circuits continue to fall with the increase in etching fineness. Thus, for a 1.2 micron technology, the supply voltage is 5 volts, whereas it is 2.5 volts for a 0.25 micron technology and 1.8 volts for a 0.18 micron technology. Consequently, placed with this technological trend, it is becoming increasingly necessary to use voltage multipliers in order to be able to benefit from voltages higher than the supply voltages, so that logic devices can, for example, be effectively controlled with logic signals whose high-state level is high enough.
However, the conventional physical parameters of electronic components, particularly the threshold voltage, have decreased less than the supply voltages and consequently represent a higher percentage of the supply voltage the higher the etching fineness. Thus, by way of indication, for a 1.2 micron technology, the nominal threshold voltage of a transistor represents 15% of the supply voltage, whereas it represents 30% of this supply voltage for a 0.18 micron technology.
Furthermore, these physical parameters are increasingly limiting the performance of circuits, and in particular make voltage multipliers less effective.
These drawbacks will now be more clearly understood upon examining FIG. 1 which shows a voltage multiplier device of the prior art.
This voltage multiplier device VMD of the prior art conventionally comprises an input terminal IT for receiving an input voltage, an output terminal OT for delivering an output voltage increased with respect to the input voltage, and a capacitor PC, usually called by those skilled in the art a "pumping capacitor", a first terminal T1 of which is connected to the output terminal OT and a second terminal T2 of which is connected to the input terminal IT.
The VMD device also includes means for charging the capacitor PC. These charging means conventionally consist of two complementary insulated-gate field-effect transistors, referenced TR1 and TR2, connected in series between a first supply terminal ST1 and the first terminal T1 of the capacitor PC. In the rest of the text, these two complementary transistors will be referred to by the name "charging transistors". Here, the first charging transistor TR1 is a p-channel transistor (PMOS transistor), the source S1 of which is connected to the first supply terminal ST1 which is connected in this case to the supply voltage Vdd. The substrate BK1 of this transistor TR1 (also referred to by the name "bulk") is conventionally connected to the source S1. The drain D1 of this first charging transistor is connected to the drain D2 of the second charging transistor TR2 which is in this case an n-channel transistor (nMOS transistor). The substrate BK2 of this second charging transistor is conventionally connected to ground and its source S2 is connected to the first terminal of the capacitor PC and consequently to the output terminal OT.
The voltage multiplier VMD also includes means for discharging the pumping capacitor PC. These discharging means are formed here by a transistor called a "discharging transistor", TR3, which in this case is an nchannel transistor. The drain D3 of this transistor TR3 is connected to the first terminal T1 of the pumping capacitor. Its substrate BK3 is conventionally connected to ground and its source S3 is connected to the second supply terminal ST2 which in this case is connected to ground.
The operation of such a voltage multiplier device is as follows.
During a first phase of charging the pumping capacitor PC, the charging transistors TR1 and TR2 are turned on by applying suitable control voltages to the respective gates G1 and G2 of these transistors and the discharging transistor TR3 is turned off by applying a suitable control voltage to the gate G3.
The second terminal T2 of the pumping capacitor is, for example, grounded and the capacitor PC charges due to the rise in voltage of the node T1 up to the value Vdd-Vt, where Vt denotes the threshold voltage of the nMOS transistor TR2 (it has been assumed here that the control voltage on the gate G2 was equal to Vdd).
This charging phase is followed by a voltage multiplication phase in which an input voltage, for example the supply voltage Vdd, is delivered to the second terminal T2 of the capacitor and an output voltage Vout, increased with respect to the input voltage, is recovered at the first terminal T1 of the capacitor. More specifically, the output voltage Vout is given by the formula (I): EQU Vout=Vdd-Vt+.alpha.Vdd=Vdd(1+.alpha.)-Vt (I)
in which .alpha. denotes a coefficient which in practice is less than 1 because of the presence of stray capacitances (this is because in the absence of stray capacitances the coefficient a would be 1).
Moreover, those skilled in the art know that the threshold voltage Vt of a field-effect transistor, in particular the transistor TR2, is defined by the formula (II): EQU Vt=Vt.sub.0 (1+.beta.) (II)
in which Vt.sub.0 denotes the nominal threshold voltage and .beta. denotes a coefficient representative of the substrate effect applied to the transistor.
More specifically, the substrate effect is manifested in an nMOS transistor by biasing the source of this transistor with a voltage greater than the substrate voltage. Furthermore, the greater this voltage difference the greater the coefficient .beta., and consequently the greater the threshold voltage Vt.
However, when the substrate BK2 of the transistor TR2 is connected to ground and the output voltage Vout is high, the substrate effect is large, thereby correspondingly reducing the value of this output voltage and therefore reducing the effectiveness of the voltage multiplier.
Once this voltage multiplication phase has been completed, the pumping capacitor PC is discharged by turning the transistor TR3 on, and then the cycle starts over again.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.